For example, FIG. 2 in Patent Document 1 illustrates a structure in which, each of differential pairing transistors is configured of four partial transistors, these eight partial transistors are symmetrically arranged in a region of “four rows×two columns”, and a dummy transistor is arranged in a region outside the arrangement region. In this manner, variations in process uniformly affect both of the differential pairing transistors, and therefore, device characteristics can be uniformed.
Also, FIG. 2 in Patent Document 2 illustrates a structure in which, four gates are regularly arranged on a diffusion layer region, and two gates on both outsides are for a dummy transistor and two gates therebetween are for a MOS transistor with a two-finger structure. This two-finger MOS transistor is for a tail current source in a differential amplifying circuit, a portion between the two gates is taken as a drain and each portion outside the two gates is taken as a source. Two dummy transistors located on both sides of the tail-current MOS transistor share the source of the tail-current MOS transistor. Their sources and drains are wired, and besides, their gates are wired to the drain of the tail-current MOS transistor, so that each dummy transistor becomes a capacitative element which is connected to the drain of the tail-current MOS transistor (that is, a common node of the differential amplifying circuit). These dummy transistors contribute to a reduction of variations in manufacture of MOS transistors, and besides, contribute to stabilization of the common node of the differential amplifying circuit. Therefore, performance in a small area can be improved.
Further, Patent Document 3 describes a structure in which, each of pairing elements configuring a differential circuit is independently formed in a diffusion layer region, and dummy elements are arranged in a vacant space in a periphery of these elements. In this manner, an input offset can be decreased, and besides, variations in dimension in the process can be decreased, so that the characteristics of the differential circuit with a designed value can be obtained.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2001-274258
Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2006-286990
Patent Document 3: Japanese Patent Application Laid-Open Publication No. H11-234109